Courtesy Takushi Tanaka: From low level electronic components (transistors, resistors) to higher level function blocks (operations amplifier, phase locked loop)....
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IF Computer > MINERVA > Example Programs > Applications > CircuitAnalysis

CircuitAnalysis

Courtesy Takushi Tanaka: From low level electronic components (transistors, resistors) to higher level function blocks (operations amplifier, phase locked loop).

This beautiful program is part of the DCSG project by Prof Takushi Tanaka of Fukuoka Institute of Technology. It is an example of the use of Prolog for analysis, synthesis, and manipulation of engineering languages; here, the language of electronic circuits. A Definite Clause Set Grammar given in rules.min is used to denote in 40 rules how components can be combined to larger functional blocks.

The program shown here works in two steps: First, from the grammar rules a parser for electronic circuits is generated. Second, the parser reads the electronic circuit and tries to account for all its components, i.e. from the parts it finds a meaningful explanation for the electronic function of the circuit as a whole.

The example circuit cd67.min (data), cd67.jpg (diagram) as given consists of 60 components.

The program circuit_analysis.min that runs the parser on the example circuit and finds 3326 meaningful functional units X in the circuit with the query

	?- cd67(Circuit), subset(X,Circuit,Rest).
and identifies the complete circuit as X = "Phase Locked Loop" functional block with the query
	?- cd67(Circuit), subset(X,Circuit,[]).
Analysis takes a few minutes processing time.

References

[1] Takushi Tanaka: "Definite-Clause Set Grammar: A Formalism for
    Problem Solving", Journal of Logic Programming, Vol.10, No.1,
    pp,1-17 (1991).
[2] Takushi Tanaka: "Parsing Electronic Circuits in a Logic Grammar",
    IEEE Trans. on Knowledge and Data Engineering, Vol.5, No.2,
    pp.225 -239 (1993).

Author

Dr. Takushi Tanaka
Prof. of Computer Science
Fukuoka Institute of Technology
3-30-1, Wajiro-Higashi, Higashi-ku,
Fukuoka 811-02, Japan
e-mail: tanaka@fit.ac.jp
http://www.fit.ac.jp/~tanaka

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document: http://www.ifcomputer.co.jp/MINERVA/ExamplePrograms/Applications/CircuitAnalysis/home_en.html
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